Leakage current and power reduction techniques in combinational circuits

Power consumption and it’s reduction is one of the primary concerns in today’s VLSI design because of two main reasons, one is the long operating life requirement of phone battery and portable devices and second is due to increasing number of transistors on a single chip which leads to high power dissipation and it can lead to reliability and IC packaging problems. Power reduction has become an important issue in digital circuit design, especially for high performance portable devices (such as cell phones, PDAs, etc.). Thus, it is evident that methodologies for the design of high-throughput, low-power digital systems are needed. A chip’s maximum power consumption depends on its technology as well as its implementation. Due to scaling down of technology and when CMOS circuits are powered by lower supply voltages, standby leakage current becomes significant. Also threshold voltage is reduced due to scaling which leads to the increase in sub- threshold leakage current and hence there will be increase in static power dissipation. In order to reduce the static power dissipation, one has to give up the circuit performance and area of the given circuit. This project discuss about various leakage current reduction methods that will be useful for both Conventional and Gate diffusion input (GDI) logics inorder to reduce the static power, dynamic power and also consider the area by using minimum number of transistors. These all were done in 95nm technology using Tanner EDA V13.0 Tool.